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NCP5212A Single Synchronous Step-Down Controller
The NCP5212A is a synchronous stepdown controller for high performance systems battery-power systems. The NCP5212A includes a high efficiency PWM controller. A pin is provided to allow two devices in interleaved operation. An internal power good voltage monitor tracks the SMPS output. NCP5212A also features soft-start sequence, UVLO for VCC and switcher, overvoltage protection, overcurrent protection, undervoltage protection and thermal shutdown. The IC is packaged in QFN16
Features http://onsemi.com MARKING DIAGRAM
16 1 QFN16 CASE 485AP 1 N5212 ALYWG G
* * * * * * * * * * * * * * * * *
0.8% accuracy 0.8 V Reference 4.5 V to 27 V Battery/Adaptor Voltage Range Adjustable Output Voltage Range: 0.8 V to 3.3 V Synchronization Interleaving between two NCP5212As Skip mode for power saving operation at light load Lossless Inductor Current Sensing Programmable Transient-Response-Enhancement (TRE) Control Programmable Adaptive Voltage Positioning (AVP) Input Supply Feedforward Control Internal Soft-Start Integrated Output Discharge (Soft-Stop) Build-in Adaptive Gate Drivers PGOOD Indication Overvoltage, Undervoltage and Overcurrent Protections Thermal Shutdown QFN16 Package This is a Pb-Free Device
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
PGOOD
SWM
16 VIN VCC SYN EN 1 2 3 4 5 COMP
15
14
BST 13 12 VCCP DL/TRESET PGND CS+ 11 10 9 8 CS-/Vo
NCP5212A
Typical Applications
QFN16 (Top View)
ORDERING INFORMATION
Device NCP5212AMNTXG Package QFN16 (Pb-Free) Shipping 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2009
May, 2009 - Rev. 0
1
DRP/OCP
* Notebook Application * System Power
6 FB
DH 7
Publication Order Number: NCP5212A/D
NCP5212A
PGOOD SWN BST 13 IDRP/OCP Detection High Side Driver Over Current Detector AVP Control 12 VCCP DH 14
TPAD
17
16 PGOOD
15
AGND
Thermal Shutdown
OSC
VIN
1 VCC
UVLO Control UVLO Control ENABLE MASTER SLAVE OC & TRE Detection NCP5212A Control Logic, Protection, RAMP Generator and PWM Logic
VCC
2
Low Side Driver
11
DL/TRESET
PGH
UVP
SYN
3
OVP
PGL
CDIFF + - + - + - + -
10
PGND
-
+
VREF-10%
VREF-20%
EN
4
Level Control
VREF+15% DISCH
VREF+10%
Current Sense Amplifier
9
CS+
+ VREF
Error Amplifier
-
5 COMP
6 FB
7 IDRP/OCP
8 CS-/Vo
Figure 1. Detail Block Diagram
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NCP5212A
VIN
5V
PGOOD PGOOD
SWN
BST
16 VIN VCC SYN 3 EN_SKIP EN_SKIP 4 5 COMP 1 2
15
DH
VOUT
14
13 12 11 10 9 VCCP DL/TRESET PGND CS+
NCP5212A AGND
GND
6 FB
7 IDRP/OCP
8 CS-/Vo
Figure 2. Typical Application Circuit (Single Device Operation)
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NCP5212A
VIN
5V
PGOOD1 PGOOD
SWN
BST
16 VIN VCC SYN EN=VEN_Master EN 1 2 3 4 5 COMP
15
DH
VOUT1 GND1
14
13 12 VCCP DL/TRESET PGND CS+
NCP5212A AGND Master 6 FB 7 IDRP/OCP 8 CS-/Vo BST
11 10 9
PGOOD2 PGOOD
SWN
16 VIN VCC SYN EN=VEN_Slave EN 1 2 3 4 5 COMP
15
DH
VOUT2 GND2
14
13 12 VCCP DL/TRESET PGND CS+
NCP5212A AGND Slave 6 FB 7 IDRP/OCP 8 CS-/Vo
11 10 9
Figure 3. Typical Application Circuit (Dual Device Operation)
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NCP5212A
PIN FUNCTION DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Symbol VIN VCC SYN EN COMP FB IDRP/OCP CS-/Vo CS+ PGND DL/TRESET VCCP BST DH SWN PGOOD TPAD Description Input voltage used for feed forward in switcher operation. Supply for analog circuit Synchronization interleaving use. This pin serves as two functions. Enable: Logic control for enabling the switcher. MASTER/SLAVE: To program the device as MASTER or SLAVE mode at dual device operation. Output of the error amplifier. Output voltage feed back. Current limit programmable and setting for AVP. Inductor current differential sense inverting input. Inductor current differential sense non-inverting input. Ground reference and high-current return path for the bottom gate driver. Gate driver output of bottom N-channel MOSFET. It also has the function for TRE threshold setting. Supply for bottom gate driver. Top gate driver input supply, a bootstrap capacitor connection between SWN and this pin. Gate driver output of top N-channel MOSFET. Switch node between top MOSFET and bottom MOSFET. Power good indicator of the output voltage. High impendence if power good (in regulation). Low impendence if power not good. Copper pad on bottom of IC used for heat sinking. This pin should be connected to the analog ground plane under the IC.
ABSOLUTE MAXIMUM RATINGS
Rating VCC Power Supply Voltage to AGND VIN Supply to AGND High-side Gate Drive Supply: BST to SWN High-side Gate Drive Voltage: DH to SWN Low-side Gate Drive Supply: VCCP to PGND Low-side Gate Drive Voltage: DL to PGND Input / Output Pins to AGND Switch Node SWN-PGND High-Side Gate Drive/Low-Side Gate Drive Outputs PGND Thermal Characteristics Thermal Resistance Junction-to-Ambient (QFN16 Package) Operating Junction Temperature Range (Note 1) Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Symbol VCC VIN VBST-VSWN, VDH-VSWN, VCCP-VPGND, VDL-VPGND, VIO VSWN DH, DL VPGND RqJA TJ TA Tstg MSL Value -0.3, 6.0 -0.3, 30 -0.3, 6.0 Unit V V V
-0.3, 6.0 -5 V (< 100 ns) 30 V -3(DC) -0.3, 0.3 48 -40 to + 150 - 40 to + 85 - 55 to +150 1
V V V V C/W C C C -
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. 1. Internally limited by thermal shutdown, 150C min.
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NCP5212A
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =-40C to 85C, unless other noted)
Characteristics SUPPLY VOLTAGE Input Voltage VCC Operating Voltage SUPPLY CURRENT VCC Quiescent Supply Current in Master operation VCC Quiescent Supply Current in Slave Operation VCC Shutdown Current BST Quiescent Supply Current in Master Operation BST Quiescent Supply Current in Slave Operation BST Shutdown Current VCCP Shutdown Current VIN Supply Current VIN Shutdown Current VOLTAGE-MONITOR Rising VCC Threshold VCC UVLO Hysteresis Rising VIN Threshold VIN UVLO Hysteresis Power Good High Threshold Power Good High Hysteresis Power Good Low Threshold Power Good Low Hysteresis Power Good High Delay Power Good Low Delay Output Overvoltage Rising Threshold Overvoltage Fault Propagation Delay Output Undervoltage Trip Threshold Output Undervoltage Protection Blanking Time REFERENCE OUTPUT Internal Reference Voltage Vref 0.7936 0.8 0.8064 V VCCth+ VCCHYS VINth+ VINHYS VPGH VPGH_HYS VPGL VPGL_HYS Td_PGH Td_PGL OVPth+ OVPTblk UVPth UVPTblk Wake Up, Design Spec. (Note 2) (Note 2) PGOOD in from higher Vo (PGOOD goes high) PGOOD high hysteresis (PGOOD goes low) PGOOD in from lower Vo (PGOOD goes high) PGOOD low hysteresis (PGOOD goes low) After Tss, (Note 2) (Note 2) With respect to Error Comparator Threshold of 0.8 V FB forced 2% above trip threshold (Note 2) With respect to Error Comparator Threshold of 0.8 V (Note 2) 75 - 110 80 Wake Up 4.05 200 3.4 200 105 4.25 275 3.8 500 110 5 85 -5 1.25 1.5 115 1.5 80 8/fsw 85 - 120 90 4.48 400 4.2 800 115 V mV V mV % % % % ms ms % ms % s IVCC_Master IVCC_Slave IVCC_SD IBST_Master EN = VEN_Master, VFB forced above regulation point. DH, DL are open EN = VEN_Slave, VFB forced above regulation point, DH, DL are open EN = VEN_Disable, VCC = 5 V, True Shutdown EN = VEN_Master, VFB forced above regulation point, DH and DL are open, No boost trap diode EN = VEN_Slave, VFB forced above regulation point, DH and DL are open No boost trap diode EN = 0 V EN = 0 V, VCCP = 5 V EN = 5V, VIN = 27 V EN = 0 V, VIN = 27 V 1.5 1.5 2.5 2.5 1 0.3 mA mA mA mA VIN VCC 4.5 4.5 - 5.0 27 5.5 V V Symbol Test Conditions Min Typ Max Unit
IBST_Slave
0.3
mA
IBST_SD IVCCP_SD IVIN IVIN_SD
1 1 35 1
mA mA mA mA
2. Guaranteed by design, not tested in production.
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NCP5212A
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =-40C to 85C, unless other noted)
Characteristics OSCILLATOR Operation Frequency OVERCURRENT THRESHOLD Total Detection Time OCSET Detection Time INTERNAL SOFT-START Soft-Start Time VOLTAGE ERROR AMPLIFIER DC Gain Unity Gain Bandwidth Slew Rate FB Bias Current Output Voltage Swing GAIN_VEA BW_VEA SR_VEA Ibias_FB Vmax_EA Vmin_EA DIFFERENTIAL CURRENT SENSE AMPLIFIER CS+ and CS- Common-mode Input Signal Range Input Bias Current Input Signal Range Offset Current at IDRP [(CS+)-(CS-)] to IDRP Gain VCSCOM_MAX CS_IIB CS_range IDRP_offset IDRP_GAIN (IDRP/((CS+) - (CS-))) BW_CS IDRP_Max (CS+) - (CS-) = 0 V (CS+) - (CS-) = 10 mV, V(IDRP) = 0.8 V TA = 25C TA = -40C to 85C Refer to AGND -100 -70 -1.0 0.475 0.425 20 2.5 0.525 3.5 100 70 1.0 0.575 0.625 V nA mV mA mA/mV mA/mV MHz V Isource_EA = 2 mA Isink_EA = 2 mA 3.3 3.5 0.15 0.3 (Note 2) (Note 2) COMP PIN TO GND = 100 pF (Note 2) 88 15 2.5 0.1 dB MHz V/ms mA V V TSS 0.9 1.1 1.3 ms TDETECT T_OCDET Period of FB shorts to ground before SS (Note 2) 1.26 1.09 1.92 2.21 1.47 ms ms FSW 270 300 330 kHz Symbol Test Conditions Min Typ Max Unit
Current-Sense Bandwidth Maximum IDRP Output Voltage
At -3dB to DC Gain (Note 2) (CS+) - (CS-) = 70 mV, Isource drops to 95% of the value when V(IDRP) = 0.8 V
Minimum IDRP Output Voltage IDRP Output current OVERCURRENT PROTECTION SETTING Overcurrent Threshold (OCTH) Detection Current Ratio of OC Threshold over OCSET Votlage OCSET Voltage for Default Fixed OC Threshold OCSET Voltage for Adjustable OC Threshold OCSET Voltage for OC Disable Default Fixed OC Threshold
IDRP_Min I_IDRP -1.0
0 35
V mA
I_OCSET
Sourced from OCP before soft-start, Rocset = 16.7 kW is connected from OCP to AGND or FB V((CS+) - (CS-)) / V_OCSET (Note 2) Rocset v 2 kW is connected from OCP to AGND or FB Rocset = 8.3 ~ 25 kW is connected from OCP to AGND or FB Rocset w 35 kW is connected from OCP to AGND or FB (CS+) - (CS-), Pin OCP is shorted to AGND or FB
21.6
24
26.4
mA
K_OCSET VOCSET_DFT VOCSET_ADJ VOCSET_DIS V_OCTH_DFT
0.1 100 200 720 35 40 45 600
- mV mV mV mV
2. Guaranteed by design, not tested in production.
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NCP5212A
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =-40C to 85C, unless other noted)
Characteristics OVERCURRENT PROTECTION SETTING Adjustable OC Threshold V_OCTH ((CS+)-(CS-)) (CS+) - (CS-), During OC threshold, set a voltage at pin OCP VOCSET = 200 mV VOCSET = 600 mV 15 52 20 60 25 68 mV Symbol Test Conditions Min Typ Max Unit
GATE DRIVERS DH Pull-HIGH Resistance DH Pull-LOW Resistance DL Pull-HIGH Resistance DL Pull-LOW Resistance DH Source Current DH Sink Current DL Source Current DL Sink Current Dead Time RH_DH RL_DH RH_DL RL_DL Isource_DH Isink_DH Isource_DL Isink_DL TD_LH TD_HL Negative Current Detection Threshold SWN source leakage Internal Resistor from DH to SWN CONTROL SECTION EN Logic Input Voltage for Disable VEN_Disable Set as Disable Hysteresis EN Logic Input Voltage for MASTER Mode EN Logic Input Voltage for SLAVE Mode EN Source Current EN Sink Current PGOOD Pin ON Resistance PGOOD Pin OFF Current SYNC CONTROL SYNC pin leakage SYNC frequency Pulse Width Clock Level Low Clock Level High SYNC Driving Capability SYNC Source Current OUTPUT DISCHARGE MODE Output Discharge On-Resistance Threshold for Discharge Off Rdischarge Vth_DisOff EN = 0 V 0.2 20 0.3 35 0.4 W V ISYNC_LK F_SYNC PW_SYNC V_CLKL V_CLKH SYNC_CL ISYNC Set as Slave Mode, SYNC = 5 V (Note 2) (Note 2) (Note 2) (Note 2) Set as Master Mode, load capacitor between SYNC and GND (Note 2) SYNC shorts to ground 1.2 416 0 5 20 20 1 uA MHz ns V V pF mApp VEN_Master VEN_Slave Set as Master Mode Set as Slave Mode Hysteresis IEN_SOURCE IEN_SINK PGOOD_R PGOOD_LK VEN = 0 V VEN = 5 V I_PGOOD = 5 mA 100 1 0.7 150 1.7 2.4 100 1.0 200 1.95 2.65 175 1.3 250 2.25 2.9 250 0.1 0.1 V mV V V mV mA mA W mA NCD_TH ISWN_SD R_DH_SWN 200 mA Source current 200 mA Sink current 200 mA Source current 200 mA Sink current (Note 2) (Note 2) (Note 2) (Note 2) DL-off to DH-on (Note 2) DH-off to DL-on (Note 2) SWN - PGND, at EN = 5 V EN = 0 V, SWN = 0 V (Note 2) 100 1 1 1 0.5 2.5 2.5 2.5 5 20 20 -1 1 W W W W A A A A ns ns mV mA kW
2. Guaranteed by design, not tested in production.
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NCP5212A
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =-40C to 85C, unless other noted)
Characteristics TRE SETTING TRE Threshold Detection Current I_TRESET Sourced from DL in the short period before soft-start. (Rtre = 47 kW is connected from DL to GND Internal TRE_TH is set to 300 mV Internal TRE_TH is set to 500 mV TRE is Disabled Rtre w 75 kW (Note 2) Rtre = 44 - 50 kW (Note 2) Rtre v 25 kW (Note 2) 7.2 8 8.8 mA Symbol Test Conditions Min Typ Max Unit
Detection Voltage for TRE Threshold Selection
VDL_TRE_1 (Default) VDL_TRE_2 VDL_TRE_3
500 300 0
600
700 450 250
mV
TRE Comparator Offset Propagation Delay of TRE Comparator THERMAL SHUTDOWN Thermal Shutdown Thermal Shutdown Hysteresis
TRE_OS TD_PWM
(Note 2) (Note 2)
10 20
mV ns
Tsd Tsdhys
(Note 2) (Note 2)
150 25
C C
2. Guaranteed by design, not tested in production.
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NCP5212A
TYPICAL OPERATING CHARACTERISTICS
0.83 0.82 VFB Vref VOLTAGE (V) 0.81 0.80 0.79 0.78 0.77 -40 VCC PIN SHUTDOWN CURRENT (nA) -15 10 35 60 85 200 150 100 50 0 -50 -100 -40
-15
10
35
60
85
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
Figure 4. Vref Voltage vs Ambient Temperature
315 310 305 300 295 290 285 -40 IDRP_Gain (mA/mV) 0.80 0.70 0.60 0.50 0.40 0.30
Figure 5. VCC Shutdown Current vs Ambient Temperature
FSW SWITCHING FREQUENCY (kHz)
-15
10
35
60
85
0.20 -40
-15
10
35
60
85
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
Figure 6. Switching Frequency vs Ambient Temperature
40 30 20 10 0 -10 -20 -40 43 42 41 40 39 38
Figure 7. IDRP Gain vs Ambient Temperature
BST PIN SHUTDOWN CURRENT (nA)
DEFAULT FIX OC THRESHOLD (mV) -15 10 35 60 AMBIENT TEMPERATURE (C) 85
37 -40
-15 10 35 60 AMBIENT TEMPERATURE (C)
85
Figure 8. BST Shutdown Current vs Ambient Temperature
Figure 9. Default Fix OC Threshold vs Ambient Temperature
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NCP5212A
TYPICAL OPERATING CHARACTERISTICS
Top to Bottom: EN, SWN, Vo, PGOOD
Top to Bottom: EN, SWN, Vo, PGOOD
Figure 10. Powerup Sequence
Figure 11. Powerdown Sequence
Top to Bottom: SWN_Slave, Vo_Slave, SWN_Master, Sync_clk
Top to Bottom: SWN_Slave, Vo_Slave, SWN_Master, Sync_clk
Figure 12. From Unsync to Sync
Figure 13. From Sync to Unsync
Top to Bottom: SWN, Vo, Io
Figure 14. Typical Transient
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DETAILED OPERATING DESCRIPTION
General
The NCP5212A synchronous stepdown power controller contains a PWM controller for wide battery/adaptor voltage range applications The NCP5212A includes power good voltage monitor, soft-start, overcurrent protection, undervoltage protection, overvoltage protection and thermal shutdown. The NCP5212A features power saving function which can increase the efficiency at light load. It is ideal for battery operated systems. The IC is packaged in QFN16.
Control Logic
The internal control logic is powered by VCC. The device is controlled by an EN pin. The EN pin serves two functions. When voltage of EN is below VEN_Disable, it shuts down the device. When the voltage of EN is at the level of VEN_Master, the device is operating as Master mode. When voltage level of EN is at VEN_Slave, the device is operating as Slave mode. It should be noted that no matter the device is operating either at Master or Slave mode, the device is operating in the manner of auto power saving condition such that it operates as skip mode automatically at light load. When EN is above VEN_Disable, the internal Vref is activated and power-on reset occurs which resets all the protection faults. Once Vref reaches its regulation voltage, an internal signal will wake up the supply undervoltage monitor which will assert a "GOOD" condition. In addition, the NCP5212A continuously monitors VCC and VIN levels with undervoltage lockout (UVLO) function.
Single Device Operation
Top to Bottom: VIN AC Voltage, SWN_Slave, SWN_Master
Figure 15. Two Devices are Unsynchronized
The device is operating as single device operation when the SYNC pin is pull to ground. Under this configuration, the device will use the internal clock for normal PWM operation.
Dual Device Operation (Master/Salve Mode)
Top to Bottom: VIN AC Voltage, SWN_Slave, SWN_Master
Figure 16. Two Devices are in Interleaved Operation Transient Response Enhancement (TRE)
The device is operating as Master/Slave mode if two devices are tied up together. (Detail configuration please see the application schematic) One device is served as Master and another one is served as Slave. Once they already, they are synchronized to each other and they are operating as "interleaved" mode such that the phase shift of their switching clocks is 180. It has the benefit that the amount of ripple current at the VIN will be lower and hence lesser bulk capacitors at VIN to save the confined PCB space and material cost. Figure 15 and Figure 16 show the difference when the devices are operating independently (unsynchronized) and operating at interleaved mode (Synchronized). It can be seen that at the unsynchronized condition, the system is obviously noisy because of high ripple voltage at VIN (ripple voltage directly reflects the amount of ripple current at VIN). Once the devices are operating at interleaving mode, the overall VIN ripple current is significantly reduced.
For the conventional PWM controller in CCM, the fastest response time is one switching cycle in the worst case. To further improve transient response in CCM, a transient response enhancement circuitry is implemented inside the NCP5212A. In CCM operation, the controller is continuously monitoring the COMP pin output voltage of the error amplifier to detect the load transient events. The functional block diagram of TRE is shown below.
COMP R C internal TRE_TH + +
TRE
Figure 17. Block Diagram of TRE Circuit
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Once the large transient occurs, the COMP signal may be large enough to exceed the threshold and then TRE "flag" signal will be asserted in a short period which is typically around one normal switching cycle. In this short period, the controller will be running at high frequency and hence has faster response. After that the controller comes back to normal switching frequency operation. We can program the internal TRE threshold (TRE_TH). For detail please see the electrical table of "TRE Setting" section. Basically, the recommend internal TRE threshold value is around 1.5 times of peak-to-peak value of the COMP signal at CCM operation. The higher the internal TRE_TH, the lower sensitivity to load transient. The TRE function can be disable by setting the Rtre which is connecting to DL/TRE pin to less than 25 kW. For system component saving, it is usually set as default value, that is, Rtre is open (w75 kW) and internal TRE_TH is 300 mV typical.
Adaptive Voltage Positioning (AVP)
For applications with fast transient currents, adaptive voltage positioning can reduce peak-to-peak output voltage deviations due to load transients. With the use of AVP, the output voltage allows to have some controlled sag when load current is applied. Upon removal of the load, the output voltage returns no higher than the original level, just allowing one output transient peak to be cancelled over a load step up and release cycle. The amount of AVP is adjustable. The behaviors of the Vo waveforms with or without AVP are depicted at Figure 20.
Vo With AVP Vo Without AVP
Figure 20. Adaptive Voltage Positioning
Vo Rt FB Rb Rocp IDRP/OCP L Rs1 Cs CS+ + DCR Rs2 CS- Gi + Vref - + COMP
IDRP
Top to Bottom SWN, Vo, Transient Signal
Figure 18. Transient Response with TRE Disable
Figure 21. Configuration for AVP Function
The Figure 21 shows how to realize the AVP function. A current path is connecting to the FB pin via Rocp resistor. Rocp is not actually for AVP function, indeed, Rocp is used for OCP threshold value programming. The IDRP/OCP pin has dual functions: OCP programming and AVP. At the IDRP/OCP pin, conceptually there is a current source which is modulated by current sensing amplifier. The output voltage Vo with AVP is:
V O + V O0 * I O * R LL
(eq. 1)
Top to Bottom SWN, Vo, Transient Signal
Where Io is the load current, no load output voltage Vo0 is set by the external divider that is:
V O0 + 1 ) Rt Rb * V ref
(eq. 2)
Figure 19. Transient Response with TRE Enable
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NCP5212A
The load line impendence RLL is given by:
R LL + DCR * Gain_CS * Rt * Rs2 Rs1 ) Rs2
(eq. 3)
Where DCR is inductor DC resistance. Gain_CS is a gain from [(CS+)-(CS-)] to IDRP Gain (At electrical table, the symbol is IDRP_GAIN), the typical value is 0.525 mA/mV. The AVP function can be easily disable by shorting the Rocp resistor into ground. From the equation we can see that the value of "top" resistor Rt can affect the amount of RLL, so it is recommended to define the amount of RLL FRIST before defining the compensation component value. And if the user wants to fine tune the compensation network for optimizing the transient performance, it is NOT recommend to adjust the value of Rt. Otherwise, both transient performance and AVP amount will be affected. The following diagram shows the typical waveform of AVP. Note that the Rt typical value should be above 1 kW.
Top to Bottom : SWN, Vo, PGOOD, Io
Figure 23. Overcurrent Protection
The NCP5217A uses lossless inductor current sensing for acquiring current information. In addition, the threshold OCP voltage can be programmed to some desired value by setting the programming resistor Rocp.
Vo Rt Rb + - Vref IDRP FB + COMP
IDRP/OCP L DCR Rs1 Cs Rocp CS+ Rs2 CS-
+
Gi
Without AVP Vo
Top to Bottom: SWN, Vo, Transient Signal
Rt Rb Rocp
Figure 22. Typical waveform of AVP Over Current Protection (OCP)
FB
+
COMP IDRP
IDRP/OCP L DCR Rs1 Cs CS+ Rs2 CS-
+ - Vref
The NCP5212A protects power system if over current event occurs. The current is continuously monitored by the differential current sensing circuit. The current limit threshold voltage VOCSET can be programmed by resistor ROCSET connecting at the IDRP/OCP pin. However, fixed default VOCSET can be achieved if ROCSET is less than 2 kW. If the inductor current exceeds the current threshold continuously, the top gate driver will be turned off cycle by cycle. If it happens over consecutive 16 clock cycles time (16 x 1/fSW), the device is latched off such that top and bottom gate drivers are off. EN resets or power recycle the device can exit the fault. The following diagram shows the typical behavior of OCP.
+
Gi
With AVP
Figure 24. OCP Configuration
It should be noted that there are two configurations for Rocp resistor. If Adaptor Voltage Position (AVP) is used, the Rocp should be connected to FB pin. If AVP is not used, the Rocp should be connected to ground. At the IDRP/OCP pin, there is a constant current(24 mA typ.) flowing out during the programming stage at system start up. This is used to
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NCP5212A
sense the voltage level which is developed by a resistor Rocp so as to program the overcurrent detection threshold voltage. For typical application, the Vocth is set as default value(40 mV typ) by setting Rocp = 0 W, or directly short the IDRP/OCP pin to ground. It has the benefit of saving one component at application board. For other programming values of Vocth, please refer to the electrical table of "Overcurrent Protection Setting" section.
Guidelines for selecting OCP Trip Component
fault. The following diagram shows the typical waveform when OVP event occurs.
1. Choose the value of Rocp for Vocth selection. 2. Define the DC value of OCP trip point(IOCP_DC) that you want. The typical value is 1.5 to 1.8 times of maximum loading current. For example, if maximum loading is 10 A, then set OCP trip point at 15 A to 18 A. 3. Calculate the inductor peak current (Ipk)which is estimated by the equation:
I pk + IOCP_DC ) V o * (V IN * V o) 2 * V IN * f SW * L o
(eq. 4)
Top to Bottom : SWN, DL, Vo, PGOOD
Figure 25. Overvoltage Protection Undervoltage Protection (UVP)
4. Check with inductor datasheet to find out the value of inductor DC resistance DCR, then calculate the RS1, RS2 dividing factor k based on the equation:
k+ V octh I pk * DCR
(eq. 5)
5. Select CS value between 100 nF to 200 nF. Typically, 100 nF will be used. 6. Calculate Rs1 value by the equation:
Rs1 + L k * DCR * Cs k * Rs1 1*k
(eq. 6)
An UVP circuit monitors the VFB voltage to detect under voltage event. The under voltage limit is 80% (typical) of the nominal VFB voltage. If the VFB voltage is below this threshold over consecutive 8 clock cycles, an UV fault is set and the device is latched off such that both top and bottom gate drives are off. EN resets or power recycle the device can exit the fault.
7. Calculate Rs2 value by the equation:
Rs2 +
(eq. 7)
8. Hence, all the current sense components Rs1, Rs2, Cs had been found for taget IOCP_DC. 9. If Rs2 is not used (open), set k = 1, at that moment, the Ipk will be restricted by:
I pk + V octh DCR
(eq. 8) Top to Bottom : SWN, Vo, PGOOD
Overvoltage Protection (OVP)
When VFB voltage is above 115% (typical) of the nominal VFB voltage for over 1.5 ms blanking time, an OV fault is set. At that moment, the top gate drive is turned off and the bottom gate drive is turned on until the VFB below lower under voltage (UV) threshold and bottom gate drive is turned on again whenever VFB goes above upper UV threshold. EN resets or power recycle the device can exit the
Figure 26. Undervoltage Protection Thermal Shutdown
The IC will shutdown if the die temperature exceeds 150C. The IC restarts operation only after the junction temperature drops below 125C.
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NCP5212A
C28 R220 D22 C27 C26 R7 LED1 PGOOD M5 TPAD U1 16 PGOOD R21 C23 R23 C21 R2 C22 EN 1 VIN 15 SWN 14 DH 13 BST 12 R22 C29 R27 PGND 10 CS-/Vo CS+ 9 C25 R1 DL R26 M2 D21 C212 PGND PGND R25 M4 R212 R24 R224 PGOOD SWN R29 C24 DH M1 M3 L1 C1 C2 C216 D23 PGND VIN
R28
VOUT PGND J21
VCCP
+5V AGND
2 VCC 3 SYN 4 EN COMP
DL/TRESET 11 NCP5212A DRP/OCP 7 FB R211 R214 C215 R215 R223 J2 1 3
JP3 R216 JP2 COMP C214
5 R213
FB 6
SYNC
8
C213
C3 2 PGND AGND
R210 1-2 = OCP Only 3-2 = OCP + AVP
Figure 27. Demo Board Schematic
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NCP5212A
DEMO BOARD BILL OF MATERIAL BOM (See next tables for compensation network and power stage)
Designator U1 R1 R2 R7 R21 R22 R23 R26 R27 R28 R29 R210 R212 R216 R220 R223 R224 C3 C21 C22 C23 C24 C25 C26 C27 C28 C29 C212 C216 M5 D21 D22 D23 SYNC, J21 JP2, JP3, J2, EN, FB, COMP, DH, DL, SWN, PGOOD, PGND, PGND LED1 +5V, AGND, GND, VOUT, VIN, PGND Qty 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 12 MLCC Chip Capacitor Temp Char: X5R, $20% Rate V = 25 V Power MOSFET 50 V, 200 mA Single N-Ch - 30 V Schottky Diode Vf = 0.35 V @ 10 mA - SMB SMT Straight Socket Pin Header Single Row Description Single Synchronous Stepdown Controller Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $1% Chip Resistor Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $1% Chip Resistor, $5% - MLCC Chip Capacitor, $20% Temp Char: X5R, Rate V = 25 V, MLCC Chip Capacitor, $20% Temp Char: X5R, Rate V = 25 V MLCC Chip Capacitor, $10% Temp Char: X7R, Rate V = 50 V MLCC Chip Capacitor, $10% Temp Char: X7R, Rate V = 50 V MLCC Chip Capacitor Temp Char: X7R, $10% Rate V = 50 V MLCC Chip Capacitor Temp Char: X5R, $20% Rate V = 25 V MLCC Chip Capacitor Temp Char: X5R, $20% Rate V = 25 V MLCC Chip Capacitor Temp Char: X5R, $20% Rate V = 25 V MLCC Chip Capacitor Temp Char: X5R, $20% Rate V = 25 V Value - DNP 10k 1k 20 0 5.6 0 DNP 0 5.6 1k DNP 10k 0 1k 100k DNP 1 mF 1 mF 15 nF 100 nF 100 nF 10 mF 10 mF 10 mF 1 mF DNP 1 mF - DNP - DNP - - Footprint QFN 16PIN - 0603 0603 0603 0603 0603 0603 - 0603 0603 0603 0603 0603 0603 0603 0603 - 0805 0805 0805 0603 0603 1206 1206 1206 1206 - 0805 SOT-23 - SOT-23 - 5.1 x 5.1 mm Pitch = 2.54 mm Manufacturer ON Semiconductor - Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic - Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic - Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic - Panasonic ON Semiconductor - ON Semiconductor - Tyco Electonics Betamax Manufacturer P/N NCP5212MNR2G - ERJ3GEYJ103V ERJ3GEYJ102V ERJ3GEYJR200V ERJ3GEYJR00V ERJ3GEYJR5R6V ERJ3GEYJR00V - ERJ3GEYJR00V ERJ3GEYJR5R6V ERJ3EKF1001V ERJ3EKF2403V ERJ3GEYJ103V ERJ3GEYJR00V ERJ3EKF1001V ERJ3GEYJ104V - ECJ2FB1E105M ECJ2FB1E105M ECJ1VB1E153K ECJ1VB1E104K ECJ1VB1E104K ECJ3YB1E106M ECJ3YB1E106M ECJ3YB1E106M ECJ3YB1E105M - ECJ2FB1E105M BSS138L - BAT54LT1 - RS Stock# 420-5401 2211S-40G-F1
1 1
Surface Mount LED Color = Green Terminal Pin
- -
0805 f = 1.74 mm
LUMEX HARWIN
SML-LX0805GC-TR H2121-01
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17
NCP5212A
DEMO BOARD BILL OF MATERIAL (Vo = 1.1 V, Io = 18 A)
Item Component R211 R213 R214 Compensation Network R215 C213 C214 C215 M1, M3 M2, M4 L1 Power Stage & Current Sense R24 R25 C1, C2, C2A* Value 3k 68k 300 8k 24 pF 470 pF 820 pF - - 0.56 mH DNP 4k 330 uF 6 mW Tol 1% 1% 1% 1% 10% 10% 10% - - 20% - 1% 20% Footprint 0603 0603 0603 0603 0603 0603 0603 SOIC8-FL SOIC8-FL 10x11.5 mm - 0603 7343 Manufacturer Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic ON Semiconductor ON Semiconductor Cyntec - Panasonic Panasonic Sanyo Manufacturer P/N ERJ3EKF3001V ERJ3EKF6802V ERJ3EKF3000V ERJ3EKF8001V ECJ1VC1H241K ECJ1VB1H471K ECJ1VB1H821K NTMFS4821N NTMFS4847N PCMC104T-R56MN - ERJ3EKF4301V EEFSX0D331XR 2TPLF330M6
*C2A is the capacitor soldered right beside of C2.
DEMO BOARD BILL OF MATERIAL (Vo = 1.5 V, Io = 8 A)
Item Component R211 R213 R214 Compensation Network R215 C213 C214 C215 M1, M2 M3, M4 L1 Power Stage & Current Sense R24 R25 C1, C2 Value 5k 75k 1k 5.6k 9 pF 270 pF 330 pF - DNP 1 mH DNP 4.3k 220 mF 12 mW Tol 1% 1% 1% 1% 10% 10% 10% - - 20% - 1% 20% Footprint 0603 0603 0603 0603 0603 0603 0603 SO8 - 10x11.5 mm - 0603 7343 Manufacturer Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic ON Semiconductor - Cyntec - Panasonic Panasonic Sanyo Manufacturer P/N ERJ3EKF5001V ERJ3EKF7502V ERJ3EKF1001V ERJ3EKF5601V ECJ1VC1H900K ECJ1VB1H271K ECJ1VB1H331K NTMS4705N - PCMC104T-1R0MN - ERJ3EKF4301V EEFUD0D221XR 2R5TPL220MC
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NCP5212A
PACKAGE DIMENSIONS
QFN16 4x4, 0.65P CASE 485AP-01 ISSUE O
L L1 DETAIL A L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.25 0.35 4.00 BSC 2.00 2.20 4.00 BSC 2.00 2.20 0.65 BSC 0.20 --- 0.45 0.65 --- 0.15
D
A B
PIN 1 REFERENCE
2X 2X
0.15 C 0.15 C
DETAIL B
(A3)
A
0.10 C
16X
0.08 C
NOTE 4 DETAIL A 5 4
SIDE VIEW D2
8 9
A1
16X
C L
SEATING PLANE
E2
1 16X 12 16 13 16X
K
e
b 0.10 C A B 0.05 C
NOTE 3
BOTTOM VIEW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
CCC EEE CCC EEE EEE EEE
A1 DETAIL B
OPTIONAL LEAD CONSTRUCTIONS
CC CC
E
EXPOSED Cu
OPTIONAL LEAD CONSTRUCTIONS
MOLD CMPD
A3
TOP VIEW
MOUNTING FOOTPRINT*
4.30 2.25
PKG OUTLINE
1
4.30 2.25
PITCH
0.65
0.78
16X
0.35
DIMENSIONS: MILLIMETERS
16X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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19
NCP5212A/D

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